1. Field of the Invention
The invention relates to a semiconductor integrated circuit and a method for testing the same, and more particularly to a semiconductor integrated circuit including a built-in test circuit (i.e., a built-in self test circuit (BIST)) which checks frequencies at which the semiconductor integrated circuit operates, and a method for testing a semiconductor integrated circuit.
2. Description of the Related Art
A semiconductor integrated circuit 61 shown in FIG. 8 includes an input/output circuit 62, and a phase-locked loop circuit (hereinafter referred to simply as a “PLL”) 63. The semiconductor integrated circuit 61 receives inputs of signals. Each of the signals contains data and a clock superimposed thereon through RXP and RXN input terminals 65 and 66. The input terminals 65 and 66 are connected to an external device. The circuit 61 transfers parallel data 73, which is generated by a delay circuit that recovers the phase of the clock.
The input/output circuit 62 includes a receiver 67, a clock/data recovery circuit (CDR) 69, a serial-parallel converter (i.e., a serial-in parallel-out converter (SIPO)) 70, a phase comparator (i.e., a phase detector/comparator (PD)) 68 connected to an output of the receiver 67, a delay circuit 71, and a register 72.
A mass production test for the semiconductor integrated circuit 61 involves setting the values of the register 72 to system requirements; changing the phase of the clock transferred from the delay circuit 71; using the phase comparator 68 to compare a clock edge extracted from the input signal to a clock edge transferred from the delay circuit 71; and matching the clock edge transferred from the delay circuit 71 to the clock edge extracted from the input signal, thereby locking the phase.
To test a conventional semiconductor integrated circuit, a test has been performed for the range of frequencies at which the semiconductor integrated circuit operate. The test involves receiving a clock signal of a uniform frequency, and increasing the delay time of a delay line; then changing, in sequence, the logical levels of frequency control signals arranged in parallel; detecting a change to low or high level in an external signal line; and using an external device to check how the semiconductor integrated circuit functions at a specific frequency.